4timing.com, January 2002
After months of deliberation, the IEEE's Task Group G in November tentatively approved a new standard for wireless networking — 802.11g. The new standard will allow data rates as high as 54 Mbps in the 2.4 GHz spectrum, and it includes backward compatibility. Mandatory modulation schemes of the standard are complementary code keying (CCK), used in 802.11b, and orthogonal frequency division multiplexing (OFDM), used in 802.11a. According to industry experts, it is a huge win for the wireless industry for several reasons. First, it is backwards compatible with the large installed user base of over 11 million Wi-Fi products. Second, it meets our customers' demands for significant speed increases in the 2.4 GHz band, necessary for multi-channel DVD-quality video and CD-quality audio applications.
Qualcomm has announced the successful public demonstration of a wireless voice call via a third-generation (3G) universal mobile telecommunications system (UMTS)-compliant handset. The demonstration used a handset equipped with the Qualcomm CDMA technologies (QCT) MSM5200(TM) mobile station modem (MSM(TM)) wideband CDMA (WCDMA) chipset and system software.
Advanced Power Technology, Bend, Oregon, announces a definitive agreement to acquire GHz Technology, Santa Clara, CA. The acquisition is part of the company's ongoing strategy to expand its product and technology portfolio in the RF power arena through both internal development and acquisitions. The combination will position APT with the products and technology to serve a broad range of RF applications requiring RF power transistors capable of switching at frequencies from 1 MHz to 3.5 GHz.
Based on a 0.22 mm process, the new single-chip will consist of six devices ranging in density from 150,000 to 1-million system gates. The combination of its fine-grained, ASIC-like architecture and non-volatile flash configuration memory makes the devices a strong ASIC alternative. The devices are live at power up, highly secure and require no separate configuration memory, all characteristics shared by ASICs. The ProASIC Plus architecture supports popular ASIC tool flows, reducing time to market and allowing designers to migrate easily between FPGA and ASIC solutions. Additional new features include multiple PLLs, support for up to 198kbits of two-port embedded SRAM and 712 user-configurable I/Os, and improved in-system programmability. System speeds of up to 100MHz can be achieved and designers can seamlessly interface between 3.3 and 2.5V devices in a mixed-voltage environment. The ProASIC Plus family contains two advanced clock-conditioning blocks, each consisting of a PLL core, delay lines and clock multiplier/dividers. Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs. In-system programmability is supported through the IEEE standard 1149.1 JTAG interface. ProASIC Plus FPGAs are user programmed with a multi-bit key that blocks external attempts to read or alter the configuration settings.
A plug-and-play Class 2 radio, the PBA 313 01/2/3 is designed for cable replacement and other Bluetooth communication links. It needs an antenna, a 13MHz reference frequency crystal, digital control functionality and firmware to produce a complete Bluetooth link. This unit offers a solution to one of the major problems facing designers when implementing Bluetooth technology: how to cost-effectively manufacture RF products in volume. The radio operates in RF-rich environments, including those where wireless LAN technologies such as IEEE 802.11b networks are present.
RF Solutions Ltd. in UK has introduced its X2010 and X2011 transceivers, which are designed to give wireless high reliability operation at data rates of up to 20kbps over distances of typically 300 meters. Both models can be supplied with operating frequencies of either 434.075, 868 or 914.5MHz. The X2011 features an integrated PCB loop antenna for the 434 and 868MHz versions for easy integration and EMC approval. The transmitter section is a PLL design that utilizes a stable and accurate reference crystal oscillator. This results in an RF transmission with a very low frequency spread across the entire -20 to +55°C temperature range.
With a power consumption of 8W, the TZA2080 reduces network energy costs, while its jitter performance allows highly reliable data switching without the need for external re-timing logic. Providing 68x68 point non-blocking operation (simultaneous routing of multiple inputs to multiple outputs), the switch is designed for use in a wide range of switching topologies. Features include programmable input and output polarity, programmable output voltage swing (100mV to 1.6V pk-pk), power-down modes for unused inputs and 'loss-of-activity” monitoring.
The MA1110 single-port and MA1140/MA1141 quad-port transceivers target emerging Gigabit Ethernet designs operating over copper cabling. The devices, part of the Everest family, are equipped with the IntelliRate oversampling architecture, which allows the transceivers to sample at 250 MHz, which is double the normal sampling rate. By sampling at this rate, the transceivers can generate two samples per symbol, enabling better SNR, and achieve a faster start-up time. All the products conform to the 802.3, 802.3u, and 802.3ab specifications and are fabricated in a 0.18-μm process at TSMC. The single-port device is aimed at NIC cards while the quad-port devices are geared toward gigabit switches used in enterprise LANs.
The X1288 and X1286 real-time clocks have been unleashed for set-top box and router designs. The X1288 combined real-time clock/calendar functions with a 32K x 8-b EEPROM and system management building blocks. The X1286 provides the same clock/calendar functions and memory, without the supervisory functions. The clocks operate from 1.8 to 5.5 V and include an on-chip oscillator compensation feature that eliminates the need for an external RC circuit. They also feature a user-selectable output option that enables the parts to achieve a square wave of 32.768 kHz, 100 Hz, or 1 Hz out of the real-time clock.
Technologies Introduces Two New Jitter Test Instruments
Two jitter test solutions have been unleashed for design engineers building 2.5- or 10-Gbps optical networking equipment. The JS1000 allows engineers to measure electronic components and modules that are employed in optical transport networks. This instrument offers a 50-micro UI intrinsic jitter value, approximate 0.2-dB repeatability, 0.005-dB resolution, and 0.01-dB accuracy. The 71501D, on the other hand, allows designers to measure jitter at different rates. This instrument complies with the 80 MHz modulation bandwidth requirements of the ITU-T 0.172 and Bellcore GR-1377-CORE specification. It also delivers a 0.002 intrinsic jitter value.
The MAP-BSP-15 DSP is engineered for broadband systems delivering video services. The C-programmable solutions is developed using a VLIW/SIMD architecture, supports digital RGB, provides a PCI-compliant data port, and offers support for SDRAM. Running at 333 MHz, the processor is optimized for set-top boxes, media gateways, home networking equipment, and other broadband solutions.
The FIN1022 is a 2 x 2 LVDS crosspoint switch targeted at SONET/SDH, wireless base station, and multiple routing applications. The switch can be configured as a 2:1 multiplexer, a 1:2 demultiplexer, a 2:2 repeater, or a 1:2 signal splitter. The switch allows direct interfacing to LVPECL, SSTL-2, HSTL, and LVDS. It also delivers a 3.3-V operating voltage, 35-ps channel-to-channel skew, and 1.6-ns prop delay.
The HDMP-3001 has been unleashed to solve designer's quests to deliver Ethernet services over SONET links. This mapper chip is a layer 2 devices combines SONET and Ethernet functionality in the same piece of silicon, making it an ideal solution for LAN and metro access network designs. The mapper is housed in a 160-pin PQFP.
This Mercury5G chipset allows design engineers to build WLAN systems that support both the IEEE 802.11b and 802.11a specifications. The chipset includes a direct conversion dual-band radio chip and a modem/MAC chip; both fabricated using a CMOS process. The chip set supports both the AES and WEP protocols. It also delivers spectrum management functions such as transmit power control and dynamic frequency selection.
TAEC has introduced the industry's smallest RF surface acoustic wave (SAW) filters currently available. By employing chip scale packaging (CSP), Toshiba achieved a 40 percent size reduction and 60 percent weight reduction as compared to conventional RF SAW filters. In addition, the devices offer the same electrical performance as SAW Filters offered in larger packaging, giving designers a well-rounded solution for smaller form factor mobile devices. Toshiba created the new CSP SAW filters utilizing the same "Flip Chip Bonding" technology the company currently uses for its RF filters measuring 2.5 mm x 2.0mm. It a realized an even smaller package size of 2.0mm x 1.5mm for the CSP SAW filter by applying advanced approaches to the package base and sealing technology. In lieu of the ceramic cap used in RF filters, a new thin package base was developed in order to achieve an extremely low package height of 0.6mm maximum as compared to 1.0mm. To maintain strong sealing reliability and improve production efficiency, Toshiba incorporated a specific new adhesive material.