NEWS BRIEFS

4timing.com, February 2003

10-Gbit/second Transceivers Prototypes

At the International Solid-State Circuits Conference in San Francisco, papers presented describing new clock-data recovery (CDR) schemes that mesh clocks and data in the same signal while evading noise, jitter and interference problems.

Fujitsu Approach

Based on a 0.11-micron CMOS process, Fujitsu's transceiver transmits signals at 10 Gbits/s over multiple channels using a single 1.2-volt power source.  The company was able to get by with a relatively low power source by employing quasi-digital circuits known as phase interpolators instead of more power-hungry phase-locked loops (PLLs).  These circuits convert a signal into phases and synthesize it with a reference clock without the use of as oscillator, thus lowering power consumption.

NEC Approach

Based on 0.15-micron design rules, NEC's 10-Gbit/s serializer/deserializer macro uses a "half-rate" start-able-oscillator CDR scheme, where the VCO operates at just 5 GHz.  This and other techniques lets the transceiver macro consume 50 mW and take up considerably less die area than CDR circuits that rely on PLLs and phase interpolators.

Rambus Approach

Rambus Inc. described its own high-speed signaling scheme based on pulse amplitude modulation (PAM) that spans from 2.5 to 10 Gbits/s.  This technique uses multiple signaling levels as a way to extend interconnect bandwidth by trading off inter-symbol interference with received-signal power.  The macrocell reaches 10-Gbit/s speeds using a 4-PAM signaling scheme, and overcomes signal degradation by using equalizers on the transmit side and reflection-cancellation techniques on the receive side.  The technology can transmit 10-Gbit/s data over 20 inches of backplane with two connectors and two 3-inch line cards.  At these speeds, power was measured at 450 mW, according to Rambus.

Korea Research Approach

Seoul National University described a 0.18-micron CMOS test chip that can operate from 2.5 to 10 Gbits/s. The chip was designed so that it could dynamically adjust phase-detector deadband and charge-pump current as a way to stabilize loop characteristics of CDR and achieve predictable jitter. At maximum speed, the chip consumes 540 mW from a 1.8-V supply.

TriQuint Finishes Building Test Facility in China

TriQuint Semiconductor Inc., which makes chips for communications applications, said it has finished building a test facility in Tianjin China.  The facility will be operated by Sawtek Inc., a wholly owned subsidiary of TriQuint Semiconductor, to provide assembly, test, mark, tape and reel support for TriQuint's products that serve the worldwide cell phone market.   TriQuint began construction on the facility in November 2002 and completed it in February 2003.  The primary charter for the facility is to provide shorter time-to-market, local currency support, and after sales service in support of domestic Chinese communications equipment manufacturers as well as international OEMs, the company said.

Researchers in Korea Show Wireless PAN Radio Prototype

Researchers at the Korean Advanced Institute of Science and Technology have built a prototype radio that adheres to the IEEE 802.15.4 standard for wireless personal-area networks (WPANs), making it the first radio to meet the standard, the group said.

The IEEE developed the 802.15.4 WPAN standard as a low-cost alternative to Bluetooth transceivers, which are defined by the IEEE 802.15.1 standard.  Bluetooth devices are considered too expensive and consume too much power for low date-rate applications in the home automation and industrial control markets, critics say.

The Korean researchers said their 2.4-GHz coin-sized radio (which measures 8.75 mm2) costs less than a dollar.  The device is essentially a system-in-chip with monolithic structures layered on a multilevel printed-circuit board using chip-on-board connection techniques.  Housed in a plastic package, the device contains a flip-chip RF transceiver and flip-chip processor, a pc-board inductor, a full transceiver, an inverted-F patch antenna and a battery.  The processor circuitry includes a modem, processor, controller and memory.  The transceiver circuits utilize a low-IF architecture with a polyphase filter and a transistor linearization technique.  Both flip-chips are fabbed in 0.18-micron CMOS.  The device consumes 21 mW in receive mode and 30 mW in transmit mode using a 1.8-volt supply voltage.

Motorola to build CDMA Network in India

Motorola has received a $43 million contract to install a CDMA 1X network in the Indian cities of Maharashtra, Mumbai and Goa, the company said on Feb. 18.  Motorola will deploy the network by May of this year for Tata Teleservices, a private Indian company offering basic telecom services and a subsidiary of the massive Tata Group.  The network will shore up Tata's CDMA network in south India, as well as recently launched services in the capital, Delhi.

Qualcomm Team Up with China Unicom to Form Joint Venture

Qualcomm Inc. has formed a 50:50 joint venture with Chinese mobile phone service provider China Unicom to foster the adoption of code division multiple access (CDMA) wireless technology and in particular the so-called 'BREW' software platform.  The joint venture is called Unicom-BREW Wireless Technologies Ltd. and contains within the name a reference to Qualcomm's Binary Runtime Environment for Wireless.

Unicom-BREW Wireless Technologies Ltd. is expected to offer BREW promotion, training, technical support and conduct university outreach programs.  The carriers currently deploying BREW-based services include: China Unicom, KTF of South Korea, KDDI of Japan, and Verizon Wireless and ALLTEL of the United States.  More than 40 BREW-enabled handsets are available worldwide, Qualcomm said.

Antenova Introduces In-Air Mixing Antenna for Micro Basestations

Antenova Ltd. in Cannes France announced a new antenna design that may change the economics of the micro basestations used to optimize cell coverage.  Called the HDA 1000, the new antenna uses "in-air" mixing to eliminate the conventional duplexer or multicasting hardware that combines the broadcast RF carrier signals from two or more transceivers, the company says.  In addition to possibly saving several hundred dollars of hardware costs, this may eliminate some 3.6 dB of transmission power losses.

To combine carrier signals from multiple transceivers in the air, conventional antennas must be physically separated by a substantial distance to avoid cross-coupling.  For GSM frequencies, this spacing needs to be of the order of a meter.  Such an antenna separation is possible on a macro basestation, but is not typically used on micro basestations due to the aesthetic considerations and physical constraints imposed by urban and office installation locations.

Antenova's high dielectric antenna (HDA) technology makes it possible to get the required isolation with a much closer spacing between the antennas.  The use of high-dielectric ceramic materials results in a highly localized near field around the antenna.  This allows antennas to be mounted within millimeters if required, without suffering coupling effects.  Antenova's HDA 1000 design provides dual omni-directional antennas co-mounted inside a 25 x 4 x 2.7 cm (12 x 1.6 x 1 inch) case.  The HDA 1000 is designed for the GSM 1800 band and operates over the 1710 MHz to 1880 MHz frequencies.

LVDS Repeaters by Fairchild Semiconductor

Fairchild Semiconductor has expanded its LVDS interface IC portfolio with four new LVDS repeaters.  Interface products include 1:1, 2:2, 4:4 and 8:8 LVDS repeaters, which are designed to provide signal-level translation and to buffer signals traveling across backplane or cable in multiple communications applications, including SONET/SDH, base stations and multiple routing applications.  These LVDS repeaters can also be used for signal-level translation.  Their wide common-mode range allows a designer to directly interface multiple I/O standards to LVDS levels, including direct interfacing to LVPECL (low voltage positive ECL), SSTL-2 (series stub-terminated logic) and HSTL (high-speed transceiver logic).  They are said to operate at greater than 800 Mbps, allowing interfacing to STS-1, STS-3 and STS-12 levels.  End systems can achieve higher bandwidth capability with short 1.5-ns (max.) prop delay, low peak-to-peak jitter, tight 35-ps (typical) channel-to-channel skew and low power.

Single, Dual and Quad LVDS Line Receivers by Maxim

Maxim has introduced the MAX9171/MAX9172/MAX9173 single, dual, and quad LVDS line receivers with "in path" fail-safe.  The devices accept LVDS and LVPECL signals and translate them to LVTTL/LVCMOS.  All three receivers conform to the ANSI TIA/EIA-644 standard, making them suitable for minimizing power, EMI, and bit-error rates in next-generation clock/data distribution networks of cell phone base stations, central office switches, networking switches/routers, DSLAMs, and other communications equipment.  The devices operate with a single 3.3V (10 percent) supply with low current consumption 6 mA for the MAX9171, 9 mA for the MAX9172 and 15mA maximum current for the MAX9173.  They are guaranteed for a 500 Mbps data rate.  The low 30 ps (typical) pulse skew on the MAX9171/MAX9172 reduces bit errors by minimizing duty-cycle distortion.

64 bit RISC MPU Consumes 0.6W at 300 MHz by Toshiba

Toshiba's new 64-bit reduced instruction set computer microprocessor, designated TMPR4955BFG-300, is fabricated with 0.13 micron complementary metal oxide semiconductor (CMOS) process technology.  Power consumption is 0.6 watt (W) when operating at its maximum frequency of 300 megahertz (MHz).  It is targeted at embedded devices that handle large amounts of graphics data.  Features include the incorporation of a four-way set-associative large-capacity cache memory as well as the integration of an FPU that is separate from the integer logic unit, making it possible to perform integer operations and floating point operations independently.