

Quartz Crystal Oscillator: Terms and DefinitionsNominal frequency: The center or nominal frequency of a crystal oscillator. Package: Crystal oscillators are packaged in various styles from lead through holes to surface mount types. Various sizes and functions are suitable for different applications. Frequency stability: Deviation from the nominal output frequency including the frequency deviation due to manufacturing process, temperature, power source variation and load variation. The most common stabilities are ±25, ±50 and ±100 ppm. Operating temperature range: Temperature range within which output frequency stability and other electrical, environmental characteristics meet the specifications. Military: 55 °C to +125 °C; Industrial: 40 °C to +85 °C; Commercial: 0 °C to +70 °C. Frequency aging: The relative frequency change over a certain period of time. This rate of change of frequency is normally exponential in character. Typically, aging is ±5 ppm maximum over 1 year. Storage temperature: The temperature range within which the unit is safely stored without damaging or changing the performance of the unit. Oscillator output: The output of a hybrid crystal oscillator is a highly stable reference signal and it can form square wave of HCMOS or TTL level, depending on the technology of the active devices used in the circuit. Output logic: The vast majority of systems require a crystal oscillator output that is TTL compatible, CMOS compatible, ECL compatible, HCSL compatible or some combinations of logic families such as TTL/HCMOS compatible. TTL/HCMOS compatible: The oscillator is designed with ACMOS logic with driving capability of TTL and HCMOS loads while maintaining minimum logic HIGH of the HCMOS. LVPECL (Lowvoltage Positive Emittercoupled Logic): LVPECL differential outputs are typically chosen for their superior jitter performance. The standard LVPECL output option requires external biasing and proper termination of 50 to VDD2V for each side of the differential output. The primary disadvantages of this output format are increased power consumption (due to dc biasing) and incompatibility with 1.8V supplies. The primary advantage of the LVPECL signal format is jitter performance. LVPECL provides the best jitter performance because of its large swing and fast edge rates. LVDS (Lowvoltage Differential Signaling): LVDS provides a low cost, multigigabit data transfer (100 Mbps and higher) on copper cables or printed circuit boards traces. It uses differential data transmission of 300 mV. This differential signal is immune to commonmode noise, which is the primary source of system noise. The low voltage swing of 300mV decreases emissions and cross talk problems. LVDS outputs require no external biasing or termination when connected to LVDS inputs and are very powerefficient. In addition, the LVDS specification allows for significant dc biasing drift from transmitter to receiver, further simplifying systemlevel design. HCSL (HighSpeed Current Steering Logic): HCSL outputs are commonly used for PCI Express applications, such as Intel chipsets. Logic levels: Logic levels may be positive or negative. Positive logic is assumed when logic 1 level is more positive than logic 0 level, while negative logic is assumed when the logic 1 level is more negative than logic 0 level. Output HIGH voltage (V_{OH}): The minimum voltage at output logic 1 state of the oscillator under proper loading. Output LOW voltage (V_{OL}): The maximum voltage at output logic 0 state of the oscillator under proper loading. Fan out (Loads): The measure of the driving capability of an oscillator, expressed as the number of inputs that can be driven by a single output. It can be represented by an equivalent load capacitance specified at pF in CMOS logic or the number of gates in TTL load circuit consisting of diodes, load resistors, and a capacitor. If this value exceeds the maximum rated load of the oscillator, signal degradation can occur. Startup time: The startup time is specified as the time that an oscillator take to reach its specified RF output amplitude. The startup time is determined by the closed loop time constant and the loading condition of its circuit. Rise & Fall time (t_{r} & t_{f}): The rise time (t_{r}) of an oscillator is defined as the transition time of the output waveform from low stage (logic “0”) to high stage (logic “1”). The fall time (t_{f}) of an oscillator is defined as the transition time of the output waveform from high stage (logic “1”) to low stage (logic “0”). The transition time is measured at the specified level such as between 90% and 10% of the falling edge of the switching waveform for HCMOS device. Fast rise & fall time requirements can steer a user to using ECL, even for frequencies typically satisfied by HCMOS/TTL. Increasing the load will increase the rise and fall times of the device. Symmetry or Duty cycle: The measure of output waveform uniformity or the shape of the waveform, which is made up of logic “1” and logic “0” cycle times. It is defined as the ratio of the time periods of the logic 1 level (T_{H}) to the time periods of one complete cycle (T), measured at 1.4 volts for TTL logic and 50% of the peaktopeak voltage for CMOS and ECL logic. Sym = T_{H}/T x 100%. Tristate enable: By applying a command input signal to the oscillators, the output of the clock oscillators is turned off or disabled. When this feature is activated, the oscillators assume a high impedance state. This feature allows the oscillator to be isolated from the circuit upon application of a command signal. Input current and supply voltage: Input current is the amount of current drain by an oscillator in its operating condition. Different logic oscillators require different input current. Supply voltage is the voltage necessary to operate the oscillator. It is typically 5 V or 3.3 V. Phase Noise: Phase noise is a small fraction of undesirable frequency near the output frequency, and is usually expressed as the single side band (SSB) power density in a 1 Hz bandwidth at a specified offset frequency from the carrier. It is measure in dBc/Hz. Jitter: Measure of the modulation in phase or frequency of the oscillator output. Stand by function: A function built in the IC that temporary turns off the oscillator to save power. Logic “0” will enable stand by mode. The disable current at stand by mode varies from few microamperes to tens of microamperes (0.005 mA typical). Because oscillation is halted, there is a maximum of 10 ms (same amount as the startup time) before output stabilizes. Harmonic distortion: The nonlinear distortion due to unwanted harmonic spectrum component related with target signal frequency. Each harmonic component is the ratio of electric power against desired signal output electric power and expressed in terms of dBc. Harmonic distortion specification is important especially in Sine output when a clean and less distorted signal is required. Spread spectrum crystal oscillators: A spread spectrum crystal oscillator is an oscillator that has the output frequency intentionally modulated in order to reduce the EMI on the output signal. Spread spectrum crystal oscillators are best used in applications that require a reduction of EMI emissions in order to pass the regulatory bodies (such as US FCC) EMI regulations. Additionally, using a spread spectrum clock oscillator reduces the EMI at the clock source, rather than at locations later down in the clock stream. By reducing the EMI at the clock source, supplemental shielding enclosures and/or filtering components may not be required, reducing overall system costs and improving overall EMI performance. 